Ph.D.
Computer Engineering
The University of New Mexico
2016
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Faculty
Faculty
Wenjie Che
Assistant Professor
Department/Office
- Department of Electrical Engineering and Computer Science, CEA
School/College
- College of Engineering and Architecture (CEA)
Biography
Dr. Wenjie Che received his Ph.D. degree from the Department of Electrical and Computer Engineering at the University of New Mexico in 2016. He was the recipient of the best hardware demo award (2nd place) at the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2017. Dr. Che has (co)-authored 20+ papers in prestigious peer-reviewed conferences and journals such as ICCAD, HOST, FCCM and IEEE Transactions on VLSI. He holds several Provisionals that are licensed by Enthentica Inc. Dr. Che has served as the hardware demo chair in the organization committee and as a TPC member of the HOST conference 2022-present, and a session chair for ICCAD 2019. He has been a reviewer for prestigious journals and conferences including IEEE Transactions on VLSI, IEEE Transactions on CAD, IEEE Transactions on IFS, HOST, DATE. He is a member of IEEE.
Education & Expertise
Education
Expertise
Hardware Security and Trust, Hardware Software Co-Design, Artificial Intelligence Security
Academics
Academics
EECE 406/412 Advanced Digital Systems Design/Lab
Related Articles
Selected Publications
Note: Authors with "*" are students under my supervision.
[22] Omar M. Faruque*, Wenjie Che, “Enlarging Reliable Pairs via Inter-Distance Offset for a PUF Entropy-Boosting Algorithm”, accepted by 24rd IEEE International Symposium on Quality Electronic Design (ISQED), 2023. (8-page full paper).
[21] Andres Martinez-Sanchez*, Deva Borah, Wenjie Che, “A Lightweight Neighbor-Averaging Technique for Reducing Systematic Variations In Physically Unclonable Functions”, accepted by 23rd IEEE International Symposium on Quality Electronic Design (ISQED’2022), 6 pages,
[20] Xiaochen Tang, Shanshan Liu, Wenjie Che and Wei Tang, “Tampering Attack Detection in Analog to Feature Converter for Wearable Biosensor”, accepted by 2022 IEEE International Symposium on Circuits & Systems (ISCAS).
[19] R. Valles-Novo*, A. Martinez-Sanchez* and W. Che, “Boosting Entropy and Enhancing Reliability for Physically Unclonable Functions”, IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2020, pp. 1-6. (Acceptance rate: 30%)
[18] I Bow, N Bete, F Saqib, W Che, C Patel, R Robucci, C Chan, J Plusquellic, “Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity”, Cryptography, vol. 4, no. 2, 2020.
[17] J Calhoun, C Minwalla, C Helmich, F Saqib, W. Che, J Plusquellic, “Physical Unclonable Function (PUF)-Based e-Cash Transaction Protocol (PUF-Cash),” Cryptography, vol. 3, no. 3, 2019.
[16] W. Che, M. Martinez-Ramon, F. Saqib, J. Plusquellic, “Delay Model and Machine Learning Exploration of a Hardware-Embedded Delay PUF," in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018, pp. 153-158.
[15] G. Pocklassery, W. Che, F. Saqib, M. Areno and J. Plusquellic, “Self-Authenticating Secure Boot for FPGAs,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018, pp. 221-226.
[14] W. Che, F. Saqib, J. Plusquellic, "Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 4, pp. 733-743, April 2018.
[13] D. Owen Jr., D. Heeger, C. Chan, W. Che, F. Saqib, M. Areno and J. Plusquellic, “An Autonomous, Self-Authenticating and Self-Contained Secure Boot Process for FPGAs”, Cryptography (MDPI), vol. 2, no. 3, 2018.
[12] W. Che, V. K. Kajuluri, F. Saqib, J. Plusquellic, “Leveraging Distributions in Physical Unclonable Functions,” Cryptography, vol. 1, no. 3, 2017.
[11] W. Che, V. K. Kajuluri, M. Martin, F. Saqib, J. Plusquellic, “Analysis of Entropy in a Hardware-Embedded Delay PUF,” Cryptography, vol. 1, no. 1, 2017.
[10] A. S. Siddiqui, C.-C. Lee, W. Che, J. Plusquellic and F. Saqib, “Secure Intra-Vehicular Communication over CANFD”, AsianHOST, 2017, pp. 97-102.
[9] W. Che, M. Martin, G. Pocklassery, V. K. Kajuluri, F. Saqib, J. Plusquellic, “A Privacy-preserving, Mutual PUF-Based Authentication Protocol,” Cryptography, vol. 1, no. 1, 2016.
[8] W. Che, F. Saqib, J. Plusquellic, "PUF-based authentication", Proc. IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD), pp. 337-344, 2015.
[7] W. Che, J. Plusquellic, S. Bhunia, “A Non-volatile Memory Based Physically Unclonable Function without Helper Data”, ICCAD 2014, pp. 148-153.
[6] J Zhang, Y Lin, Y Lyu, RCC Cheung, W. Che, Q Zhou, J Bian, “Binding hardware IPs to specific FPGA device via inter-twining the PUF response with the FSM of sequential circuits,” In Proc. 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Seattle, USA, 2013, pp. 227.
[5] J Zhang, Y Lin, Y Lyu, G Qu, RCC Cheung, W. Che, Q Zhou, J Bian “FPGA IP protection by binding finite state machine to physical unclonable function,” in Proc. 23rd Int. Conf. Field Program. Logic Appl. (FPL), Porto, Portugal, 2013, pp. 1–4.
[4] W. Che, Y. Lin, A. Pan, J. Zhang, “A Robust Hierarchical FSM Structure for Active IC Metering,” Information Technology Journal, vol. 12, no. 6, pp. 1107-1115, 2013.
[3] A. Pan, Y. Lin, W. Che, Z. You, Y. Liu, J. Li, “A comprehensive metering scheme for intellectual property protection during both after-sale and evaluation periods of IC design,” IEICE Electronic Express, vol. 10, no. 19, pp. 1-11, 2013.
[2] J Zhang, Y Lin, W. Che, Q Wu, Y Lu, K Zhao, “Efficient verification of IP watermarks in FPGA designs through lookup table content extracting,” IEICE Electronics Express, vol. 9, no. 22, pp. 1735-1741, 2012.
[1] J Zhang, Y Lin, Q Wu, W. Che, “Watermarking FPGA Bitfile for Intellectual Property Protection,” Radioengineering, vol. 21, no. 2, pp. 764-771, 2012