Postdoctoral

Electrical and Computer Engineering
University of Connecticut
2013

Doctor of Philosophy (Ph.D.)

Electrical and Computer Engineering
University of Connecticut
2011

Master of Science (M.S.)

Computer Engineering
Sharif University of Technology
2004

Bachelor of Science (M.S.)

Computer Engineering
Iran University of Science and Technology
2001

Hardware security and trust

Internet of things security

Embedded systems design

VLSI design and testing

Computer Systems Architect

Adv. Computer Systems Architect

Introduction to Computer Networking

Introduction to VLSI Design

VLSI Design Lab

VLSI Design

Embedded Systems Design Lab

Introduction to Engineering

Visiting Faculty Research Program Award on Cyber Security Research and Applications; 2017

Howard University Proposal Incentive Program, May 2016

Howard University Summer Faculty Research Fellowship, April 2016

Howard University Research Symposium, April 2016

The most outstanding presentation in the area of physical sciences and engineering in the junior faculty/ lecturer/instructor category

Books and Book Chapters

Trusted Digital Circuits - Hardware Trojan Vulnerabilities, Prevention and Detection

Hardware Trojan Attacks and Countermeasures chapter in Fundamentals of IP and SoC Security - Design, Verification, and Debug

Digital Circuit Vulnerabilities to Hardware Trojans chapter in Hardware IP Security and Trust

Integrated Circuit Authentication: Hardware Trojans and Counterfeit Detection

Gradual-N-Justification (GNJ) to Reduce False-Positive Hardware Trojan Detection in Gate-Level Netlist

Gradual-N-Justification (GNJ) to Reduce False-Positive Hardware Trojan Detection in Gate-Level Netlist

The integrated circuit design flow is highly susceptible to hardware Trojan (HT) insertion. While there have been significant efforts to detect HTs, techniques usually demand a golden model, suffer limited scalability, or experience high false positives. This article introduced a new technique called gradual-N-justification (GNJ) to reduce false-positives HT detection in the gate-level netlist. The GNJ technique combines the signal justification and unsupervised K-means machine learning (ML) algorithm. he GNJ technique is a general technique that can be applied to a set of reported suspicious signals (SSs) in order to identify the most SSs and reduce false-positive rates (FPRs) in detecting HTs. The GNJ technique is applied to 60 different combinations of full-scan and partial-scan circuits and hard-to-detect combinational HTs.

Experimental Data Anomaly Detection at Edge Sensor Nodes Using Physics Laws

Experimental Data Anomaly Detection at Edge Sensor Nodes Using Physics Laws

We present a multivariate physics-based data anomaly detection technique in WSNs, and we implement the technique to measure the accuracy and efficiency of the proposed technique in detail. The proposed technique examines the natural relationship between various types of sensor measurements to determine the existence of any data anomaly in the node. Furthermore, the technique enables the distinction of data errors and events where a data anomaly is flagged. To evaluate the accuracy and efficiency of the technique, we have manufactured various data errors and events, measured required memory footage, and metered the amount to current consumption by a sensor node. The detailed analyses have confirmed the high accuracy and efficiency in detecting and separating data errors and environmental events.

Special Session: Countering IP Security threats in Supply chain

Special Session: Countering IP Security threats in Supply chain

The continuing decrease in feature size of integrated circuits, and the increase of the complexity and cost of design and fabrication has led to outsourcing the design and fabrication of integrated circuits to third parties across the globe, and in turn has introduced several security vulnerabilities. The adversaries in the supply chain can pirate integrated circuits, overproduce these circuits, perform reverse engineering, and/or insert hardware Trojans in these circuits. Developing countermeasures against such security threats is highly crucial. Accordingly, this paper first develops a learning-based trust verification framework to detect hardware Trojans. To tackle Trojan insertion, IP piracy and overproduction, logic locking schemes and in particular stripped functionality logic locking is discussed and its resiliency against the state-of-the-art attacks is investigated.

Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering

Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering

This article presents a rigorous step towards design-for-assurance by introducing a new class of logically reconfigurable design resilient to design reverse engineering. Based on the non-volatile spin transfer torque (STT) magnetic technology, we introduce a basic set of non-volatile reconfigurable Look-Up-Table (LUT) logic components (NV-STT-based LUTs). An STT-based LUT with a significantly different set of characteristics compared to CMOS provides new opportunities to enhance design security yet makes it challenging to remain highly competitive with custom CMOS or even SRAM-based LUT in terms of power, performance, and area. To address these challenges, we propose several algorithms to select and replace custom CMOS gates with reconfigurable STT-based LUTs during design implementation such that the functionality of STT-based components and therefore the entire design cannot be determined in any manageable time, rendering any design reverse engineering attack ineffective.